Honored Contributor
Honored ContributorNo reply from Altera yet (great support guys!)
However, I am still trying to implement audio extraction, but it doesn't work. I provide the audio extract core with vid_data, vid_clk, vid_data_valid signals (manual table 4-10), but no output is available. Since I don't need RAM, error or any other status/control/etc registers, I don't use reg_clk input to provide clock to that input. The "include clock" option is also off, so I don't use fix_clk signal, because there are no fee PLLs left for 200MHz clock. This means, that I have to use aud_clk signal feeding it with 3.072MHz signal. However, when all resets are tied to 0, all video signals are OK and 3.072MHz is provided, there are no output signals. What did I forget?
