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I will respond to my thread once again, for people facing same problems in the future.
The audio extract and audio embed cores both support I2S, AES and parallel input audio (I've managed to find out that myself).
It is better to use fix_clk option, but if You have 3.072MHz clock signal + data sync to video - both cores works without fix_clk.
reg_clk signals can be left unconnected, if You don't use status and control registers.
Those new schematic symbols for both cores are weird and it is hard to understand which pin is input and which is output.
Altera didn't bother to respond to service request yet :)
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Did Altera finally responded to SR? If Yes, then what was the answer?
Did You finally managed to make it work?
Honored Contributor
