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ADufl's avatar
ADufl
Icon for New Contributor rankNew Contributor
5 years ago

Associate an individual mif file to each RAM memory instantiated by a "generate"

Hello, I instantiate RAM memories with the following VHDL code : gen_inst_ram_0to7 : for i in 0 to 7 generate inst_ram : ram port map( address_a => w_address_a(i), address_b => w_address_b...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Best Regards,

Shyan Yew