New Contributor
Regular ContributorHi,
Sorry for the delay. Please see my update to your latest inquiries:
1. I am trying to modify the parameter "CDR_bandwidth_preset", if i configure it to high, does it improve the CDR jitter tolerance? what is the difference between high and low ? For CDR pll, increasing CDR bandwidth, whether the pll will better trace the incoming data.
[CP] For your information, the following are the discrepany between high vs low bandwidth setting. A high-bandwidth PLL/CDR provides a fast lock time and tracks jitter on the reference clock source, passing it through. A low-bandwidth PLL/CDR filters out reference clock jitter, but increases lock time.
Generally if you encounter jitter tolerance issue in your system, it is recommended for you to try with different bandwidth setting to see which one will helps.
2. another parameter is PPM detector threshold, Its description is the maximum PPM difference the CDR can tolerate between the input reference clock and the recovered clock. If I configure it to 1000, it means the recovered clock will be worse ???
[CP] For your information, value = 1000 meaning the maximum ppm difference between refclk and recovered clock that CDR can tolerate is +/-1000ppm. This is the maximum value that a CDR tolerate. It does not affect the recovered clock.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
