Occasional Contributor
Regular ContributorHi Nicole,
Thank you for the clarification. I don't aware if there is a similar issue. At this point, it does not look like the PCIe AVST problem yet. The PCIe AVST is a hard block, it will pass the TLP that received from the host to the DMA.
From the AER, does it show the completion timeout or any other error? If yes, it means that the Host does not return the completion.
If the completion package does not observe from the AVST interface, then you might need to debug it by using a PCIe protocol analyzer to confirm if the host really sent a valid completion TLP to the endpoint (FPGA).
Regards -SK
Occasional Contributor
