Forum Discussion
NZhan1
Occasional Contributor
Occasional ContributorArria10 DMA失败
使用10AX027和CPU调试PCIe时发现以下问题： 调试过程中软件驱动负责分配一块物理内存，然后把物理内存地址写入FPGA，FPGA从这个物理内存地址做DMA，读取内容。 在Xeon系列的硬件平台上的异常现象是： 当驱动分配的物理内存在4G以上时，FPGA做DMA是可以的，分配到4G以下时，FPGA发送tlp的读请求后，始终得不到响应，DMA失败。 做了以下尝试： 将FPGA及...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi Nicole,
Thank you for the clarification. I don't aware if there is a similar issue. At this point, it does not look like the PCIe AVST problem yet. The PCIe AVST is a hard block, it will pass the TLP that received from the host to the DMA.
From the AER, does it show the completion timeout or any other error? If yes, it means that the Host does not return the completion.
If the completion package does not observe from the AVST interface, then you might need to debug it by using a PCIe protocol analyzer to confirm if the host really sent a valid completion TLP to the endpoint (FPGA).
Regards -SK
NZhan1Occasional Contributor
Occasional ContributorHi SK
For AER，what kind of errors should be monitor? Timeout error and?
Is there a UG of AER errors definition can be refer to?
Is there any organizations can provide access to PCIe protocol analyzer for normal customer?
Thanks!
Regards，
Nicole
