Forum Discussion
NZhan1
Occasional Contributor
Occasional ContributorArria10 DMA失败
使用10AX027和CPU调试PCIe时发现以下问题： 调试过程中软件驱动负责分配一块物理内存，然后把物理内存地址写入FPGA，FPGA从这个物理内存地址做DMA，读取内容。 在Xeon系列的硬件平台上的异常现象是： 当驱动分配的物理内存在4G以上时，FPGA做DMA是可以的，分配到4G以下时，FPGA发送tlp的读请求后，始终得不到响应，DMA失败。 做了以下尝试： 将FPGA及...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi Nicole,
From the FPGA site, the PCIe is configured as AVST GEN2x4, then there is a custom module to connect the Avalon ST interface with the DMA? What is the memory size selected from the PCIe GUI's BAR tab?
When issue a memory write or read TLP from the Host, did you able to see the TLP appear at the Avalon ST interface?
If possible, please help to explain why is the DMA not working? Is this unable to receive the TLP from the Avalon ST interface of PCIe IP, or the PCIe IP sent incorrect packet to the DMA module in the FPGA?
Regards -SK
NZhan1Occasional Contributor
Occasional ContributorHi SK
BAR2 is enabled, type is 64-bit prefetchable memory, size is 1Mbyte-20bits.
Currently, we send a TLP with memory read request, but can’t receive CPU’s completion.
From the avst st interface, a read request is sent out.
Regards，
Nicole
