Occasional Contributor
Regular ContributorHi Nicole,
From the FPGA site, the PCIe is configured as AVST GEN2x4, then there is a custom module to connect the Avalon ST interface with the DMA? What is the memory size selected from the PCIe GUI's BAR tab?
When issue a memory write or read TLP from the Host, did you able to see the TLP appear at the Avalon ST interface?
If possible, please help to explain why is the DMA not working? Is this unable to receive the TLP from the Avalon ST interface of PCIe IP, or the PCIe IP sent incorrect packet to the DMA module in the FPGA?
Regards -SK
Occasional Contributor
