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Altera_Forum
Honored Contributor
Honored ContributorArria 2 DDR3 shared PLL
Hi, I have two DDR3 instantiations in my design. I'm low on PLL resources and I need to share the PLL of the two DDR3 inst. In the documentation I saw that the ALTMEMPHY does not support u...
Altera_ForumHonored Contributor
Honored Contributor16 transmit and receive.
The data rate is 500Mbps, it will be implemented using soft LVDS, There is no problem to use 1 external PLL for the LVDS tranceivers. The problem occures when I have no free PLL's at all. Can I derive the LVDS clock inputs from a DDR3 ALTMEMPHY PLL, or is it simply impossible ?
