Forum Discussion
agula
Occasional Contributor
5 years agoCan anybody provide any insight on this ? All example designs show Avalon ST interface to Avalon-MM with burst. I would like to know if there's an example design that up-stream DMA. Host to FPGA and FPGA to host.
Thanks!
- Rahul_S_Intel15 years ago
Frequent Contributor
The only information available is from the UG :
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avst.pdf