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TerryU's avatar
TerryU
Icon for New Contributor rankNew Contributor
7 years ago

Arria 10 Transceiver PHY parameters for CDR

Hi experts, I have reference lock issue on high speed interface mode. Then, I would need CDR-PLL related values, actually I have found some improvement with modification. However the following param...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

Dear TerryU,

Thanks for your update. Regarding the refclk input specs, you may refer to the device datasheet -> "Reference Clock Specifications" section for further details on the requirement.

Regarding the intermittent range of the cdr_pll_set_cdr_vco_speed, sorry as I do not have insight on it because there is no detail on this internal parameter in the existing documentation nor database that I can access. Sorry for the inconvenience.

By the way, if you would like to proceed using the workaround of customizing this parameter, it is recommended for you to perform thorough verification to ensure your system are working per your expectation.

Please let me know if there is any concern. Thank you.

Chee Pin

  • TerryU's avatar
    TerryU
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi Chee-san,

    I have replaced oscillator with fast edge one, rising/falling 200ps (typ), and checked performance. However result was almost same with before. So some FPGA internal analog process or QUARTUS setup might be root cause. Anyway I set optimal value for our boards, and will do qualification test. Indeed, there is a risk without technical background though.

    Thanks,

    TerryU