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TerryU's avatar
TerryU
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7 years ago

Arria 10 Transceiver PHY parameters for CDR

Hi experts, I have reference lock issue on high speed interface mode. Then, I would need CDR-PLL related values, actually I have found some improvement with modification. However the following param...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

Dear TerryU,

Thanks for your update. I have looked through your signaltap screenshot, seems like after analogreset is released, the rx_is_lockedtoref for failing board will not go high. Generally if the CDR is unable to achieve lock to ref, it may be related to the input refclk as following. You may try to further look into them as well.

1. The input refclk would need to be sourced directly from a free-running on-board oscillator with the right frequency. This is the ensure successful power up calibration.

2. Similarly, the CLKUSR would need to be sourced directly from a free-running oscillator as well for calibration.

3. Related to potential signal integrity issue, you might need to use scope to check on the eye diagram of at the input refclk pin to ensure it is meeting the specs in the device datasheet.

4. Just wonder if you wait for some more duration, will the rx_is_lockedtoref gets asserted? Or it stucks at 0.

Regarding your understanding of the rx_analogreset, yes, you are right, it affects the PMA only. Regarding the modification of analog parameters, you are also correct, it would only affect the behavior of PMA instead of logical or digital processes.

Please let me know if there is any concern. Thank you.

Chee Pin

  • TerryU's avatar
    TerryU
    Icon for New Contributor rankNew Contributor
    7 years ago

    Dear Chee-san,

    Thank you for your reply.

    I reply to your question.

    1 and 2.

    The refclk and CLKUSR are connected to input directly with close distance.

    3.

    Once I checked waveform and jitter of refclk. It would be clear. Is there specification of eye-diagram of refclk? Icouldn't fine in the usergides. Anyway it was fine clock, then I think eye-diagram should be fine.

    4.

    When I wait for a long duration more than several minutes, rx_is_lockedtoref always stay as Low.

    Signal integrity is one of possibilities, but it might be difficult revising our board.

    And this is an additional information.

    I checked the fine range of cdr_pll_set_cdr_vco_speed for my boards, and found a bit strange matter. Fine range are intermittent. 1-3, 7-10 and 16-20 are the fine range for Fine board. Regarding Fail board, those range more narrow. Then some boards failed by slight deviation . But by optimizing this value, all boards became to fine. Do you have any idea about such intermittent range? At first, I thought this value was for loop-filter on loop-gain setting, but it might be correct.

    And regarding cdr_pll_set_cdr_vco_speed_fix, it didn't affect to at least PLL-lock performance.

    Thanks

    TerryU