Arria 10 Transceiver PHY parameters for CDR

Hi Chee-san,

Thank you for your rapid response.

I have an issue on my board as reference lock issue as you would know, and those parameters are related to that.

We build production boards with using Transceiver PHY and some of boards failed (around 15%) as non-lock at reference lock, occurs at early stage after configuration. Then when I modified those parameters, the reference lock failure has been fixed. But I don't have any information about those parameters, then I did it with cut and try. So I would know about details.

And there is another strange symptom on this matter. This is trigger why I have started modification.

I was delivered design files as vendor's IP using Transceiver PHY, and verilog HDL was generated by vendor's system. And I also generated HDL from an exact same Transceiver PHY Qsys file, but those parameter's values of mine were different from vendor's one. Not only vco_speed values but, some of L/M/N counters' values are different. Vendor told me that they didn't modify any parameters.

My generated HDL caused 100% failures on our products. And vendor's HDL caused 15% failures as above. So I have tried to modify those values. Those vco_speed values would be automatically generated by QUARTUS system, but how are optimized to each hardware board?

Regards,

TerryU/Tetsuya