New ContributorHi,
good news:
1. I have successfully simulated design in Modelsim -> ATX PLL relocked after REFCLK is present ->o.k.
2. I have successfully downloaded design to hardware -> ATX PLL relocked after REFCLK is present ->o.k.
Thank's for your advice!
Regards
diddi1057
Regular ContributorHi,
Sorry for the delay. Regarding the simulation with the ATX PLL recalibration, the purpose of doing this is to check if the steps of recalibration is OK. In simulation, after ATX PLL achieves lock, if you trigger the recalibration, you should see ATX PLL going into recalibration and then out from recalibration and then achieve lock.
I am not sure if the model can replicate the no refclk behavior at power up. Thus, the purpose of simulation is to check the recalibration steps.
New ContributorHi,
performed new simulation:
REFCKL is stable at startup.
ATX PLL locked after 13 us -> OK
Then trigger recalibration: signal pll_cal_busy stays '0', signal pll_locked stays '1'
For ATX PLL recalibration, I performed the following steps (Intel® Arria® 10 Transceiver PHY
User Guide, §7.4.1.1)
1.Request access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
2.Read-Modify-Write 0x1 to the offset address 0x100[0] of the ATX PLL.
3.Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
Is there any register I also have to configure for ATX PLL recalibration?
