New ContributorHi,
good news:
1. I have successfully simulated design in Modelsim -> ATX PLL relocked after REFCLK is present ->o.k.
2. I have successfully downloaded design to hardware -> ATX PLL relocked after REFCLK is present ->o.k.
Thank's for your advice!
Regards
diddi1057
Regular ContributorHi,
As I understand it from your PDF, you observe an issue where ATX PLL unable to achieve lock due to no refclk present at power up. You have tested recalibration but seems not helping. With stable refclk present at power up, there PLL is locked.
To facilitate further debugging, just to check with you on the following:
1. Just wonder if you have had a chance to run through simulation with your recalibration steps to see if the ATX PLL is able to re-achieve lock?
2. Can you try to hold the ATX PLL in reset during power up, release when stable refclk is present. Then perform recalibration to ATX PLL followed by a reset.
3. Just to double check if the CLKUSR is directly sourced from a free-running and stable clock source on board?
4. Please share with me further on the steps that you have taken for recalibration ie the register writing sequence. I would like to see if can spot any anomaly.
Please let me know if there is nay concern. Thank you.
New ContributorHi,
As I understand it from your PDF, you observe an issue where ATX PLL unable to achieve lock due to no refclk present at power up. You have tested recalibration but seems not helping. With stable refclk present at power up, there PLL is locked.
Yes, correct!
To facilitate further debugging, just to check with you on the following:
1. Just wonder if you have had a chance to run through simulation with your recalibration steps to see if the ATX PLL is able to re-achieve lock?
Did not make simulation yet, will try ...
2. Can you try to hold the ATX PLL in reset during power up, release when stable refclk is present. Then perform recalibration to ATX PLL followed by a reset.
Will try that.
3. Just to double check if the CLKUSR is directly sourced from a free-running and stable clock source on board?
Yes, CLKUSR is an external free running source=100MHz, verified
4. Please share with me further on the steps that you have taken for recalibration ie the register writing sequence. I would like to see if can spot any anomaly.
recalib register writing sequence: refer to pma_pll_calibration.vhd state machine.
please hold on for some time for investigation.
Please let me know if there is nay concern. Thank you.
New ContributorHi,
1. Just wonder if you have had a chance to run through simulation with your recalibration steps to see if the ATX PLL is able to re-achieve lock?
Just made simulation:
-- Disabled Refclock for 1ms at start of Simulation
-- Then enabled Refclock
-- ATX PLL achieved lock after 13 us (without recalibration process)
Simulation takes a long time(~15 minutes for 2 ms). Wonder if the ATX PLL does also lock, when Refclock is disabled for longer time period at start of simulation(e.g. seconds)
2. Can you try to hold the ATX PLL in reset during power up, release when stable refclk is present. Then perform recalibration to ATX PLL followed by a reset.
Has no effect
New ContributorHi,
Did you get my information about the simulation of the ATX PLL ?
I have no idea about whats going on there!
