New ContributorArria 10 PCIe pld_clk vs coreclkout_hip
Hello,
Currently we have a project that has very tight latency requirement regarding PCIe. There's a 250Mhz clock driving most part of the design (let's call it user_clk). For PCIe HardIP, we follow the official example by directly connect coreclkout_hip to pld_clk. Thus, we need to run clock domain crossing in our design, which took roughly 5 cycles (20 ns) in simulation.
But recently I noticed the PCIe IP user guide mentioned that pld_clk can be driven other than coreclkout_hip .
So, I wonder if there's a already a CDC logic in Hard IP, regardless whether pld_clk is the same clock as coreclkout_hip. And we can save our cycles by connecting pld_clk to user_clk.
Thank you in advance for your help.
Best regards,
Chenyang
Hi Chenyang,
My apology for the delayed response.
Yes, according to the User Guide, the pld_clk, which is used to clock the Application and Transaction Layers, can be driven by a different clock than coreclkout_hip. Please take note of the requirements for pld_clk as stated in Section 7.2.2, Clock Summary Table 65.
For instance, if the chosen coreclkout_hip is 125 MHz and the pld_clk is sourced from another clock source, it must be equal to or greater than 125 MHz but have a maximum frequency of 250 MHz. In your case, it can be connected to a 250 MHz clock source (user_clk).
The PCIe Hard IP contains a CDC synchronizer at the interface between the PHY/MAC and the DLL layers to allow the DLL and Transaction layers to run at frequencies independent of the PHY/MAC.
Arria® 10 and Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/clock-summary.html
Thanks.
Best Regards,
Ven
