Arria 10 PCIe pld_clk vs coreclkout_hip

Hi Chenyang,

My apology for the delayed response.

Yes, according to the User Guide, the pld_clk, which is used to clock the Application and Transaction Layers, can be driven by a different clock than coreclkout_hip. Please take note of the requirements for pld_clk as stated in Section 7.2.2, Clock Summary Table 65.

For instance, if the chosen coreclkout_hip is 125 MHz and the pld_clk is sourced from another clock source, it must be equal to or greater than 125 MHz but have a maximum frequency of 250 MHz. In your case, it can be connected to a 250 MHz clock source (user_clk).

The PCIe Hard IP contains a CDC synchronizer at the interface between the PHY/MAC and the DLL layers to allow the DLL and Transaction layers to run at frequencies independent of the PHY/MAC.

Arria® 10 and Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/clock-summary.html

Thanks.

Best Regards,

Ven