Forum Discussion
I gone through the Errata and the details, from the below , I assume you are planning to use PCIe gen3 x8, in that case, the below Errata does not apply ,
And I am curious why you have to use CVP ,is there any particular reason ( only need to achieve PCIe 100ms time )
The above question is to understand the issue more
Or are you expecting me to provide the worst case analysis? on a perticular scenario
Hello Rhaul
Thank you for your reply. I will answer to your question below.
That is right, my board is PCIe gen3 x8.
I am not using CvP, instead I am using Autonomous mode in order to meet the PCIe 100ms time.
I read the Errata and it looks like PCIe gen x8 is actually affected too when using Autonomous Mode (link below page 6).
If it is not affected, would you provide some documentation on this please? As I stated, I do not control both ends of the PCIe.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/es/es-1057.pdf
Regards,
Otto