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Altera_Forum
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8 years ago

Arria 10 PCIe Gen 3 timing violations in Quartus 17.0.2

I got timing violations in Arria 10 PCIe Gen 3 design after upgrading to Quartus 17.0.2. The same design compiles without timing violations in Quartus 16. Path# 1: Setup slack is -4.551 (V...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi sols,

Upgrade to Quartus 17.1 version. The timing of PCIe have been changed a lot and most of violations are removed.

If you are using 128 bit 250 MHz clock(Gen 3 configuration of PCIe) and not seeing timing violation in PCIe, let me know as I am facing setup violations -0.5 to -0.6 in core clkout.