mem
New Contributor
5 years agoArria 10 JESD204B Interoperability Reference Design timing issues
IP core Arria 10 JESD204B AD9144-AD9625 Interoperability Reference Design uses the following attribute for register duplication :
altera_attribute of normal : architecture is "-name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; .... "
Quartus 19.1 ignores the register duplication attribute and we cannot get the required timing. All the failing paths have the following node as a starting point :
u_jesd204b_ed_qsys|jesd204b_subsystem_0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
We tried several ways to convince Quartus to automatically duplicate registers in these paths, but it keeps ignoring all settings for register duplication.
Is there an attribute suitable for Arria 10 for register duplication?