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mem
New Contributor
5 years agoArria 10 JESD204B Interoperability Reference Design timing issues
IP core Arria 10 JESD204B AD9144-AD9625 Interoperability Reference Design uses the following attribute for register duplication :
altera_attribute of normal : architecture is "-name PHYSICAL_SYNTHE...
KennyT_altera
Super Contributor
5 years agoAny reason that you want to duplicate those register? Are this for timing closure? If yes, can you send us a screenshot of the timing violation.
Usually you can see the duplication failure in the fitter/synthesis reports. Can you check on it? it will show the failing reason. But I think this feature only exist in the latest Q20.4, can you upgrade your Quartus to latest version?