Arria 10 "HPS GMII to SGMII PCS Bridge IP" ports differ from "SGMII PCS IP"

Some context:

I am designing for an Arria 10 SX FPGA, Quartus Prime Pro Edition, and I need an SGMII interface

The embedded peripherals user guide mentions connecting the HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge IP and the Triple-Speed Ethernet intel FPGA IP as a method for the HPS to use SGMII.

The latter can be configured to operate in 1000BASE-X SGMII PCS ONLY mode, where the bridge comes in to connect it to the HPS GMII interface.
The bridge IP has a clock enable interface that it is to receive from the 1000BASE-X SGMII PCS IP. The documentation of the 1000BASE-X SGMII PCS IP also mentions the clock enable signal in section 6.1.12.3. However the clock enable port is missing from the 1000BASE-X SGMII PCS IP.

The parameter for enabling the clock enable signal within the IP is greyed out as its applicable only when the Triple-Speed Ethernet IP is used as a MAC.

Platform Designer also throws out a warning that the clock enable signal of the bridge IP must be connected to something

My question(s)
Since the clock enable is an input of the bridge, can I just connect it to/set it logic high? Or will it not work since the bridge IP expects it to be driven by the PCS IP?

Any other work-arounds?

Thanks for the help