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HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

Arria 10 GX Native PHY IP - Multiple protocols with Lane bonding requirements in a single TxR Bank

Hi, I am targeting Arria 10 GX 570 FPGA for custom protocol development using Transceivers. I am using Bank 1C primarily for PCie x2 (as this bank contains PCIe Hard IP). So PCIe will use channel...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


As I understand it, you have some inquiries related to the placement of channels within a XCVR bank of A10 device. Just to check with you what is the TX PLL used for the PCIex2? If you are using CMU PLL, you are left with only 3 channels for DP (2 left if you are using CMU PLL).


Regarding the bonding, there should be no issue to have two bonded groups within the same XCVR bank as there are two MCGBs. However, it is recommended for you to create a simple test design and run through Fitter compilation to check against internal placement rules.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin