Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Arria 10 GX Dev Kit - EMIF Controller Avalon Memory Mapped Slave

Hi, I am designing user logic to access DDR4 Memory on Arria 10 GX FPGA Development Kit. I instantiated EMIF in Qsys. It has following parameters: DQ width: 72 Row address width: 15 Co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hmm. What do you have the Address Ordering option set to on the Controller tab in the parameter editor?