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DM38's avatar
DM38
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1 year ago
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Arria 10 EMIF Simulation - Memory Clock Frequency

Hello,

I am attempting to simulate the Arria 10 EMIF with a DDR4 memory model but am running into some issues. I cannot get the EMIF to generate the expected DDR4 clock frequencies.

For example, I have loaded the "Arria 10 GX FPGA Development Kit with DDR4 HILO" preset and selected the corresponding "Target Development Kit" under the "Example Designs" tab. This should generate a 1066.667 MHz memory clock from a recommended 266.667 MHz reference clock. However, in simulation I end up with a 1059.322 MHz memory clock even though the reference clock is the expected 266.667 MHz value. This is causing the vendor's DDR4 memory model to select different timing parameters, which results in memory violations and errors.

I have tried various memory clock frequencies, EMIF configurations, and recommended/non-recommended reference clock frequencies without luck. It seems like whatever I try always generates a memory clock that does not have the expected frequency. It is close, but never the exact frequency.

The EMIF does assert its 'local_cal_success' signal indicating that it is calibrating properly.

Perhaps I am not configuring the IP properly on my end or I have a misunderstanding? Is there a reason that the EMIF's PLL is not creating the expected memory clock frequency?

The EMIF is being generated via Platform Designer in Quartus Prime Standard 21.1.1.

Memory
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    1 year ago

    Hello,


    The configuration for the related clock is set in the IP file.

    You need to change certain value to get the desired clock.

    You can look into file path "emif_0_example_design\sim\ed_sim\altera_emif_211\sim\ed_sim_altera_emif_211_*".

    And then go to line 1451-1455, where are the value:

    • PLL_SIM_VCO_FREQ_PS (944)
    • PLL_SIM_PHYCLK_0_FREQ_PS (1888)
    • PLL_SIM_PHYCLK_1_FREQ_PS (3776)
    • PLL_SIM_PHYCLK_FB_FREQ_PS (3776)
    • PLL_SIM_PHY_CLK_VCO_PHASE_PS (118)


    Change the value to :

    • PLL_SIM_VCO_FREQ_PS (938)
    • PLL_SIM_PHYCLK_0_FREQ_PS (1876)
    • PLL_SIM_PHYCLK_1_FREQ_PS (3752)
    • PLL_SIM_PHYCLK_FB_FREQ_PS (3752)
    • PLL_SIM_PHY_CLK_VCO_PHASE_PS (117)



    Regards,

    Adzim


4 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    Thank you for submitting your question in Intel Community.

    I'm Adzim, application engineer will assist you in this case.


    I may need some clarification on the problem that you've seen for debugging purpose.

    Please let me know about the information in point below:

    • Are you able to provide some snapshots of the waveform of the clock signal?
    • What is the other issue that you're facing that causing by this clock?
    • Can you share the clock report from Timing Analyzer?


    Regards,

    Adzim


    • DM38's avatar
      DM38
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi Adzim,

      • Are you able to provide some snapshots of the waveform of the clock signal?

      Here is a screenshot of the waveforms in simulation with appropriate flags to determine the clock frequencies. You can see that 'pll_ref_clk' has a frequency of 266.667 MHz and 'mem_clk' has a frequency of 1059.322 MHz.

      • What is the other issue that you're facing that causing by this clock?

      If the clock is not generated with the expected clock frequency, then the memory model from our vendor will not work properly. For example, the memory model uses standard operating speeds for DDR4. It configures itself based on the memory clock that is driving the model, which is 'mem_ck' and 'mem_ck_n' in this case. However, since these clocks are not being properly generated (non-ideal or non-expected frequencies), then the memory model changes its timing characteristics to a different speed.

      In this case, we should expect 'mem_ck' to be a 1066.667 MHz clock, but the EMIF IP is generating a 1059.322 MHz clock. This is causing the timing characteristics of the DDR4 model to be configured for a 933 MHz clock or datarate of 1866. Without a proper clock then the memory model cannot set its timing properties correctly.

      • Can you share the clock report from Timing Analyzer?

      Here is the clock report from the Timing Analyzer. However, I would like to reiterate that what I'm trying to accomplish is strictly in simulation at the moment. The 'ddr3_emif_new' is just the original name of the IP that I generated. It was originally going to be DDR3 but I have since switched it to DDR4. So, disregard its name as I can assure you that it is a DDR4 EMIF.

      Furthermore, the 'emif_0_core_usr_clk' looks good at 266.67 MHz, but I expect that the 1067.24 MHz clocks should be 1066.67 MHz.

      Thanks

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    The configuration for the related clock is set in the IP file.

    You need to change certain value to get the desired clock.

    You can look into file path "emif_0_example_design\sim\ed_sim\altera_emif_211\sim\ed_sim_altera_emif_211_*".

    And then go to line 1451-1455, where are the value:

    • PLL_SIM_VCO_FREQ_PS (944)
    • PLL_SIM_PHYCLK_0_FREQ_PS (1888)
    • PLL_SIM_PHYCLK_1_FREQ_PS (3776)
    • PLL_SIM_PHYCLK_FB_FREQ_PS (3776)
    • PLL_SIM_PHY_CLK_VCO_PHASE_PS (118)


    Change the value to :

    • PLL_SIM_VCO_FREQ_PS (938)
    • PLL_SIM_PHYCLK_0_FREQ_PS (1876)
    • PLL_SIM_PHYCLK_1_FREQ_PS (3752)
    • PLL_SIM_PHYCLK_FB_FREQ_PS (3752)
    • PLL_SIM_PHY_CLK_VCO_PHASE_PS (117)



    Regards,

    Adzim


    • DM38's avatar
      DM38
      Icon for New Contributor rankNew Contributor
      1 year ago

      Adzim,

      Adjusting these parameters seem to have fixed the issue. However, my IP file was not at the file path you provided. Instead, it was located at "<DESIGN_NAME>/altera_emif_211/sim/<DESIGN_NAME>_altera_emif_211_*".

      I still don't quite understand why these parameters are not adjusted whenever the IP simulation files are created. In my opinion the user should not have to alter the IP files to get the expected clock frequency once it has been generated in Platform Designer. Maybe this is a bug and could be fixed in newer versions of Quartus? Without your help I would not have known where to look.

      I attempted to generate the EMIF in Quartus Prime Pro 23.2 and I suffered the same results. So, it doesn't seem like it is just Quartus Prime Standard 21.1.1 that has this issue.

      I appreciate your help in resolving this issue. Getting the correct memory clock frequency allowed the vendor's memory model to properly set its timing configuration.

      Thank you for your time and consideration.