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DM38's avatar
DM38
Icon for New Contributor rankNew Contributor
2 years ago
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Arria 10 EMIF Simulation - Memory Clock Frequency

Hello, I am attempting to simulate the Arria 10 EMIF with a DDR4 memory model but am running into some issues. I cannot get the EMIF to generate the expected DDR4 clock frequencies. For example...
Memory
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    2 years ago

    Hello,


    The configuration for the related clock is set in the IP file.

    You need to change certain value to get the desired clock.

    You can look into file path "emif_0_example_design\sim\ed_sim\altera_emif_211\sim\ed_sim_altera_emif_211_*".

    And then go to line 1451-1455, where are the value:

    • PLL_SIM_VCO_FREQ_PS (944)
    • PLL_SIM_PHYCLK_0_FREQ_PS (1888)
    • PLL_SIM_PHYCLK_1_FREQ_PS (3776)
    • PLL_SIM_PHYCLK_FB_FREQ_PS (3776)
    • PLL_SIM_PHY_CLK_VCO_PHASE_PS (118)


    Change the value to :

    • PLL_SIM_VCO_FREQ_PS (938)
    • PLL_SIM_PHYCLK_0_FREQ_PS (1876)
    • PLL_SIM_PHYCLK_1_FREQ_PS (3752)
    • PLL_SIM_PHYCLK_FB_FREQ_PS (3752)
    • PLL_SIM_PHY_CLK_VCO_PHASE_PS (117)



    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,


Thank you for submitting your question in Intel Community.

I'm Adzim, application engineer will assist you in this case.


I may need some clarification on the problem that you've seen for debugging purpose.

Please let me know about the information in point below:

  • Are you able to provide some snapshots of the waveform of the clock signal?
  • What is the other issue that you're facing that causing by this clock?
  • Can you share the clock report from Timing Analyzer?


Regards,

Adzim


  • DM38's avatar
    DM38
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi Adzim,

    • Are you able to provide some snapshots of the waveform of the clock signal?

    Here is a screenshot of the waveforms in simulation with appropriate flags to determine the clock frequencies. You can see that 'pll_ref_clk' has a frequency of 266.667 MHz and 'mem_clk' has a frequency of 1059.322 MHz.

    • What is the other issue that you're facing that causing by this clock?

    If the clock is not generated with the expected clock frequency, then the memory model from our vendor will not work properly. For example, the memory model uses standard operating speeds for DDR4. It configures itself based on the memory clock that is driving the model, which is 'mem_ck' and 'mem_ck_n' in this case. However, since these clocks are not being properly generated (non-ideal or non-expected frequencies), then the memory model changes its timing characteristics to a different speed.

    In this case, we should expect 'mem_ck' to be a 1066.667 MHz clock, but the EMIF IP is generating a 1059.322 MHz clock. This is causing the timing characteristics of the DDR4 model to be configured for a 933 MHz clock or datarate of 1866. Without a proper clock then the memory model cannot set its timing properties correctly.

    • Can you share the clock report from Timing Analyzer?

    Here is the clock report from the Timing Analyzer. However, I would like to reiterate that what I'm trying to accomplish is strictly in simulation at the moment. The 'ddr3_emif_new' is just the original name of the IP that I generated. It was originally going to be DDR3 but I have since switched it to DDR4. So, disregard its name as I can assure you that it is a DDR4 EMIF.

    Furthermore, the 'emif_0_core_usr_clk' looks good at 266.67 MHz, but I expect that the 1067.24 MHz clocks should be 1066.67 MHz.

    Thanks