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DM38's avatar
DM38
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Arria 10 EMIF Simulation - Memory Clock Frequency

Hello, I am attempting to simulate the Arria 10 EMIF with a DDR4 memory model but am running into some issues. I cannot get the EMIF to generate the expected DDR4 clock frequencies. For example...
Memory
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    1 year ago

    Hello,


    The configuration for the related clock is set in the IP file.

    You need to change certain value to get the desired clock.

    You can look into file path "emif_0_example_design\sim\ed_sim\altera_emif_211\sim\ed_sim_altera_emif_211_*".

    And then go to line 1451-1455, where are the value:

    • PLL_SIM_VCO_FREQ_PS (944)
    • PLL_SIM_PHYCLK_0_FREQ_PS (1888)
    • PLL_SIM_PHYCLK_1_FREQ_PS (3776)
    • PLL_SIM_PHYCLK_FB_FREQ_PS (3776)
    • PLL_SIM_PHY_CLK_VCO_PHASE_PS (118)


    Change the value to :

    • PLL_SIM_VCO_FREQ_PS (938)
    • PLL_SIM_PHYCLK_0_FREQ_PS (1876)
    • PLL_SIM_PHYCLK_1_FREQ_PS (3752)
    • PLL_SIM_PHYCLK_FB_FREQ_PS (3752)
    • PLL_SIM_PHY_CLK_VCO_PHASE_PS (117)



    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,


The configuration for the related clock is set in the IP file.

You need to change certain value to get the desired clock.

You can look into file path "emif_0_example_design\sim\ed_sim\altera_emif_211\sim\ed_sim_altera_emif_211_*".

And then go to line 1451-1455, where are the value:

  • PLL_SIM_VCO_FREQ_PS (944)
  • PLL_SIM_PHYCLK_0_FREQ_PS (1888)
  • PLL_SIM_PHYCLK_1_FREQ_PS (3776)
  • PLL_SIM_PHYCLK_FB_FREQ_PS (3776)
  • PLL_SIM_PHY_CLK_VCO_PHASE_PS (118)


Change the value to :

  • PLL_SIM_VCO_FREQ_PS (938)
  • PLL_SIM_PHYCLK_0_FREQ_PS (1876)
  • PLL_SIM_PHYCLK_1_FREQ_PS (3752)
  • PLL_SIM_PHYCLK_FB_FREQ_PS (3752)
  • PLL_SIM_PHY_CLK_VCO_PHASE_PS (117)



Regards,

Adzim


DM38's avatar
DM38
Icon for New Contributor rankNew Contributor
1 year ago

Adzim,

Adjusting these parameters seem to have fixed the issue. However, my IP file was not at the file path you provided. Instead, it was located at "<DESIGN_NAME>/altera_emif_211/sim/<DESIGN_NAME>_altera_emif_211_*".

I still don't quite understand why these parameters are not adjusted whenever the IP simulation files are created. In my opinion the user should not have to alter the IP files to get the expected clock frequency once it has been generated in Platform Designer. Maybe this is a bug and could be fixed in newer versions of Quartus? Without your help I would not have known where to look.

I attempted to generate the EMIF in Quartus Prime Pro 23.2 and I suffered the same results. So, it doesn't seem like it is just Quartus Prime Standard 21.1.1 that has this issue.

I appreciate your help in resolving this issue. Getting the correct memory clock frequency allowed the vendor's memory model to properly set its timing configuration.

Thank you for your time and consideration.