Arria 10 EMIF for HPS IP "user logic" clock confusion

I am designing for an Arria 10 SX, using Quartus Prime Pro Edition

In order to connect the HPS to an external DDR memory, we can use the Arria 10 EMIF for HPS IP.

Within you can specify the memory clock frequency, while the clock rate of the "user logic" is supposed to be half of that.

There is however no "user logic" clock input to the IP, nor is there an AXI/Avalon MM interface connected to it that has an associated clock. The HPS is the one communicating with the IP so the "user logic" clock that is mentioned must be one within the HPS itself.

Reading the HPS technical reference manual shows that the L3 interconnect is connected to the SDRAM controller, so is "user logic" clock supposed to be the internal "L3 Clock Frequency"?

Or can I assume, since the HPS is the one doing all the communicating, that the clock relationship between the HPS and the HPS EMIF IP is handled automatically? It would be very nice if the only thing I had to consider is the memory frequency and the PLL reference clock of the IP.

I found a design made for a devkit that uses the HPS EMIF IP, and the value that the "user logic" clock was supposed to have(based on the memory frequency) did not exist anywhere in the design.

Thanks for the help