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Mathis1's avatar
Mathis1
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Arria 10 EMIF for HPS IP "user logic" clock confusion

I am designing for an Arria 10 SX, using Quartus Prime Pro Edition In order to connect the HPS to an external DDR memory, we can use the Arria 10 EMIF for HPS IP. Within you can specify the memory ...
Memory
  • KianHinT_altera's avatar
    KianHinT_altera
    1 year ago

    Hi

    I'm sorry for the delay in getting back as it has been awhile on this case and I'm just checking whether you have resolve the issue at your end?

    You're correct on this, the clock relationship between HPS and EMIF IP is handled automatically, just need to configure the memory settings in EMIF IP. Just some further information to connect the HPS to EMIF IP

    Once again sorry for the delay in getting back

    Thanks

    Regards

    Kian

KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks

regards

Kian