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New Contributor

3 years ago

Arria 10 DDR4 IP - Using Hyperlynx DDRx Batch Wizard With Failed Simulation Results

Hello, Device: 10AX066K2F40E1HG We are designing a DDR4 LRDIMM interface for the above device using the EMIF IP. We have a board layout, and we are attempting to complete simulation to verify...

Hyperlynx_DDR_Report.rar21.1 MB

AdzimZM_Altera

Regular Contributor

3 years ago

Hi ConnorSousa,

Thank you for submitting your question in Intel Community.

I'm Adzim, application engineer will assist you in this thread.

You can refer to Arria 10 simulation guidance flow to simulate the board simulation.

Link: https://community.intel.com/t5/FPGA-Wiki/Arria-10-EMIF-Simulation-Guidance/ta-p/735201

I think you can take the value and use it to configure the EMIF IP.
Timing closure can be done in the Quartus software.

Regards,

Adzim

hghuyho

New Contributor

2 hours ago

Hi,

I am trying to find documentation on how to use the Channel Loss Calculation Tool for Arria 10 DDR4 EMIF.

The "Arria 10 EMIF Simulation Guidance" link referenced above appears to be unavailable/redirected, and I cannot find the document on the current Altera website.

Could you please provide an updated link or any documentation related to the Channel Loss Calculation Tool?

Thanks.

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Arria 10 DDR4 IP - Using Hyperlynx DDRx Batch Wizard With Failed Simulation Results

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