mvemp
New Contributor
7 years agoArria 10 DDR4 external memory interface
I am designing my IP in OpenCL. However, I am trying to analyse the maximum vector length of data which can be fetched from DDR4 present on Arria 10 GX board.
Where can I find the IP responsible for fetching data from DDR4. Is there a hard IP present on Arria 10 chip wrt DDR4? What is bitwidth between DDR4 and memory controller?