Forum Discussion
mvemp
New Contributor
New ContributorArria 10 DDR4 external memory interface
I am designing my IP in OpenCL. However, I am trying to analyse the maximum vector length of data which can be fetched from DDR4 present on Arria 10 GX board. Where can I find the IP responsible fo...
HRZ
Frequent Contributor
Frequent Contributor1) 128 MB is probably a typo. I am sure the Hard IP supports at least up to 8 GB per DIMM, probably even more.
2) The physical interface between the FPGA and each DDR3/4 memory DIMM is 64 bits (72 bits with ECC). The theoretical peak bandwidth per DIMM is (64 bits x memory clock). e.g., it will be ~17 GB/s (15.9 GiB/s) per DDR4-2133 MHz DIMM which is typically used on Arria 10 boards.
