Aria II GX ALTGX Serdes issue-Serdes Expert needed

Maybe there is someone out there who can help with this...

We are using an Aria II GX device. We have a 150 MHz diff clock coming into a refclock location. I/O standard is the 1.5V PCML. This input clock is needed to feed into a xcvr for the high speed protocol, but is also our only input clock that we can use to plumb into a PLL to get other key clocks for the rest of the system.

Here is what happens:

Scenario 1: Take the clock directly into a PLL rather than the xcvr and routed one of the PLL outputs to our xcvr in our IP. This totally bombs saying that it can't route the refclock this way to feed into the serdes. It synthesized fine though. We know the IP will work though if we bring a clock in on a clk line other than the refclks because this is how it was proven on the development board. Clock was fed directly to the PLL and then to the IP.

Scenario 2: A suggestion was made to create a second xcvr outside of our IP and take the clock out of the xcvr (tx_clkout), feed it into a PLL and then take a PLL output into our IP. Results were a GXB xmiter channel PMA atom error making it unroutable.

Any other suggestions?

pinscore