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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

API calls failed while running PCIe DMA transfer example design

Hi, I was working the PCIe DMA transfer example design for Arria 10. I have added a counter custom IP which counts upto 1000, and An Avalon FIFO IP with the design. My intention is to write the data...
Memory
Pcie
Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Wincent,

Please do not close the ticket as we are still working on it. Sorry for bit delay in response and now trying to catch up to the pace.

Did you able to capture the LTSSM signal from Signal tap ? just to ensure the PCIe is able to link up.

No we could not capture the LTSSM signal from Signal Tap at first place. Will retry it and update you ASAP.

Did you connect the PCIe external power connector to 6-pin 12V DC power connector in the FPGA to avoid FPGA damage due to insufficient power ?

Yup absolutely! we did connect the external power connector.

The API call failure I mentioned before is that happened when Adzim provided some modified VHDL code for the PCIe_DMA transfer example design + Avalon FIFO + counter (basically he tested altered the signal connectivity). While programmed with that modified design, I got API call failure.

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Sijith,

The API call failure I mentioned before is that happened when Adzim provided some modified VHDL code for the PCIe_DMA transfer example design + Avalon FIFO + counter (basically he tested altered the signal connectivity). While programmed with that modified design, I got API call failure.

>> Can you file another forum case and select the "catagory" as EMif so that Adzim can take loop back on the API failure ?

Regards,
Wincent_Intel