Any reference design of ALT2GXP transceiver ip..........................

I'm not sure how different the ALT2GX component is relative to the Stratix IV GX ALTGX components, however, the following application note is pretty good:

http://www.altera.com/literature/an/an553.pdf

The cal_blk_clk on the Stratix IV has its timing requirements specified in the handbook, so the Stratix II GX should have it specified too. Something around 50MHz should be fine.

Cheers,

Dave

Thank you very much Sir for the reply,

I was waiting for the reply.....

I will have a look at the pdf....

I am using the Stratix II GX PCie board.......for high speed serial communication

You can find example designs on Altera's FTP site: ftp://ftp.altera.com/outgoing/siigx_demo_designs/ (ftp://ftp.altera.com/outgoing/siigx_demo_designs/)

I got it from our FAE for Belgium: Armin Faems - Arrow Central Europe GmbH

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You can find example designs on Altera's FTP site: ftp://ftp.altera.com/outgoing/siigx_demo_designs/

I got it from our FAE for Belgium: Armin Faems - Arrow Central Europe GmbH

--- Quote End ---

--- Quote Start ---

You can find example designs on Altera's FTP site: ftp://ftp.altera.com/outgoing/siigx_demo_designs/

I got it from our FAE for Belgium: Armin Faems - Arrow Central Europe GmbH

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Thank you very much Sir,

Its very useful link :):):):)