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Altera_Forum
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15 years ago

altsyncram simulating issue (single port RAM core)

Hi, I'm using Altera's core: single port RAM , which includes the component "altsyncram". when loading modelsim i get the following warning: Warning: (vsim-3473) Component instance "alts...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

When creating the RAM with Megawizard, it should create a *my_ram*.vhd file.

You need to compile this file. Otherwise, modelsim doesn't know anything about the component you are declaring.

(sorry for the confusion about altsyncram.vhd)

Cheers