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Altera_Forum
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9 years ago

altsyncram simulating, data changes on failing edge

I'm simulating altsyncram with Modelsim for Cyclone V. I use altsyncram instantiated as ROM. INCLUDE "altsyncram.inc"; FUNCTION mROM_256x18_1port( clock, address ) returns( q ); PARAMETERS ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

After changing 

always# 1 clk = ~clk;

to 

always# 10 clk = ~clk;

Data bus updates 1 ps after rising edge of clock.