New ContributorALTPLL Output Error
I am porting a number of legacy systems created for a Cyclone II chip to a MAX10 ( 10M50DAF484C6GES) using Quartus Prime v17.1. The legacy systems have a variety of clocks that were originally created using counters and as much as possible I want to migrate the clock generation into PLLs. Some of the required clock frequencies are so low that the IP Wizard tells me that they cannot be implemented in the PLL and I understand that. For one frequency however, 10KHz, the wizard says it is valid and that the PLL can be configured to produce it but in simulation the output is not working. I am using a 50MHz input clock for the PLL ... all higher frequencies simulate fine. Am I doing something wrong or is the Wizard wrong when it tells me that it can create the 10KHz clock? Thanks.
