New Contributor
Regular ContributorHi,
The PLLs are not really designed to get such a low frequency
As per datasheet of cyclone II & Max 10 we can't generate frequency of 10 Khz.
Yes, you can configure the pll for low frequency without any error but actual frequency implemented is different, even lock will be not be asserted practically.
Can check the same from altera PLL IP try by giving output clock of 10Khz you may see actual frequency in text box is different.(alt_pll is same as altera_pll)
You can write a simple clock divider and generate required frequency.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards,
Anand Raj Shankar
