ALTPLL LOCK Generation

Hello everyone,

I am new to Quartus Tool. In one of my application I am using ALTPLL Megacore for generating High frequencys. To test my design I have two sets of testcases.

1. Tx testcases

2. Rx testcases

In simulation, If I select all testcases for TX, it is running fine. Similarly for RX testcases.

But If I select one each from both the test sets, my PLL is not locking again for second testcase even though the first testcase was successfully completed. clock is still there at the input of the PLL.

Remember, In each testcase, I am resetting and Initializing the DUT and providing the required information.

Thanks & Regards