ALTPLL for SDRAM

Hi,

I'm totaly inexperienced with FPGA, Quartus II, SoPC Builder and the whole stuff.

I started with the Altera tutorial Introduction_to_the_Altera_SOPC_Builder and using_the_SDRAM. Helped me to get started but now i have some questions.

First of all, for the system I want to create, i only need NIOS II and SDRAM. I noticed in the SDRAM tutorial that i probably will need a PLL. Now I read some datasheets and dokumentations, also searched in this forum, but didn't found the answer.

How do I get the right timing for PLL? I found following caldulation:

Max. lag = min(read lag, write lag)

Max. lead = min(read lead, write lead)

with

Read lag = T[SUB]O[/SUB][SUB]H[/SUB](sdram) - T[SUB]H[/SUB](FPGA)

Write lag = T[SUB]CLK [/SUB]- T[SUB]CO_MAX[/SUB](FPGA) - T[SUB]ds[/SUB](SDRAM)

Read lead = T[SUB]clk[/SUB] - T[SUB]hz[/SUB](SDRAM) - T[SUB]su[/SUB](FPGA)

Write lead = T[SUB]co_min[/SUB](FPGA) - T[SUB]dh[/SUB](SDRAM)

Is that right? I found the timing parameters for SDRAM on my board (is42s1632od-7tl) but can't find anything for the FPGA. I'm using DE2-115 Cyclone 4. Please, tell me if I'm on the wrong way, just want to understand this stuff.

PS: sorry for my english