AltPll Dynamic phase shift state machine

Hi,

The statemachine is working fine. I have tested it with signal tap.below you find the code.

library ieee;

use ieee.std_logic_1164.all ;

use ieee.std_logic_arith.all ;

entity dynamic_input is

port (

clk : in std_logic ;

choose_op : in std_logic_vector ( 1 downto 0 ); -- "01" to shift down the phase,"10" to shift up the phase and others no effect

phase_counter_sel_in : in std_logic_vector ( 2 downto 0 );-- for selecting output clock to be shifted

phase_counter_sel_out : out std_logic_vector ( 2 downto 0 );

phase_up_down : out std_logic ;-- when '1' shifts phase up '0' shifts down

phasestep : out std_logic ;--to enable phase shift process

phasedone : in std_logic ;

--scan_clk : out std_logic ;

--state_out : out std_logic_vector (1 downto 0 )

);

end entity dynamic_input;

architecture behaviour of dynamic_input is

type state is ( init , phase_up , phase_down , wait_up , wait_down , wait_shiftend , wait_phasedone );

signal pr_state : state ;

signal next_state : state := init ;

begin

--scan_clk <= clk ;

phase_counter_sel_out <= phase_counter_sel_in ;

process ( clk )

begin

if ( clk = '0' and clk'event ) then

pr_state <= next_state ;

end if ;

end process ;

process ( pr_state )

begin

case pr_state is

when init =>

--set initial values to the dynamic parameters--

phasestep <= '0' ;

phase_up_down <= '0' ;

if ( choose_op = "10" ) then

next_state <= phase_up ;

elsif ( choose_op = "01" ) then

next_state <= phase_down ;

else

next_state <= init ;

end if ;

-----------------------------------

when phase_up =>

phasestep <= '1' ;

phase_up_down <= '1' ;

next_state <= wait_up ;

-----------------------------------

when phase_down =>

phasestep <= '1' ;

phase_up_down <= '0' ;

next_state <= wait_down ;

-----------------------------------

when wait_up =>

phasestep <= '1' ;

phase_up_down <= '1' ;

next_state <= wait_phasedone ;

-----------------------------------

when wait_down =>

phasestep <= '1' ;

phase_up_down <= '0' ;

next_state <= wait_phasedone ;

-----------------------------------

when wait_phasedone =>

if ( phasedone = '0' ) then

phasestep <= '0' ;

next_state <= wait_shiftend ;

end if ;

-----------------------------------

when wait_shiftend =>

if ( phasedone = '1' ) then

next_state <= init ;

end if ;

-----------------------------------

end case ;

end process ;

end behaviour ;