ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Hi Frank,

Thank you very much for your prompt answer!

I have tried connecting all three clocks (c0, c1, and c2) to the physical pins, and used c3 as the SignalTap clock. I also ran the TCL command you suggested in the TCL window—thank you for sharing that. Below is the fitter PLL summary:

clock0	1	1	50.0 MHz	0 (0 ps)	3.75 (208 ps)	50/50	C0
clock1	1	1	50.0 MHz	0 (0 ps)	3.75 (208 ps)	50/50	C1
clock2	1	1	50.0 MHz	0 (0 ps)	3.75 (208 ps)	50/50	C2
clock3	4	1	200.0 MHz	0 (0 ps)	15.00 (208 ps)	50/50	C3

As shown, the counters have been correctly assigned to the clocks.

Unfortunately, the behavior still seems unusual. I have attached a SignalTap screenshot where I added the three clocks to visualize the waveforms. As you can see, the c0 clock is phase-shifted relative to c1 and c2, even though the PLL phasecounterselect value I chose is 2 to phase shift c2 instead of c0, as indicated in the screenshot. This observation is in agreement with the oscilloscope measurements of the physical signals.

c0 and c1 are still shifting in opposite directions, even after connecting all clock outputs to the pins and applying the TCL command.

Apologies if I have overlooked something trivial, and thank you in advance for your time and valuable assistance!

Best regards,

Heyang