Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi ,
I am having a project with EP2AGX125EF35C4 as my FPGA and MT41J64M16LA-15E as my SDRAM device. In SOPC builder design, I have taken DDR3 SDRAM controller with ALTMEMPHY. In selected memory preset I have choosen MT41J64M16LA-15E. Now I have changed my FPGA device from EP2AGX125EF35C4 to EP2AGX125EF35I5. DDR3 device is MT41J64M16LA-15EITB. In short, I have migrated my project from commercial grade to Industrail grade. I am getting error as Timing requiements not met and DDR Timing requiements not met. Please tell me, What changes should be done to meet DDR3 Timing requirements if I am migrating my project from use of EP2AGX125EF35C4 as FPGA to EP2AGX125EF35I5 as FPGA.