ALTMEMPHY port replication/DDIO_OUT WYSIWYG invalid splitter fan out

I actually just did this today. Mrjpharris, you are correct, they are not at the top level They are buried many levels in. I found them at the ddr3_controller_phy_alt_mem_phy.v level. And yes I went through all the brutal work of bringing out the signals for the other RAMs in the RANK. What I did was start with mem_we_n signal found his driver, and duplicated the instance, renamed it, and brought the output signal (of new name) out all the way through the top to hook up at device pins. Example:

Original WE driver:

ddr3_controller_phy_alt_mem_phy_ac# (

.POWER_UP_HIGH (1),

.DWIDTH_RATIO (DWIDTH_RATIO)

) we_n_struct (

.clk_2x (ac_clk_2x),

.reset_2x_n (1'b1),

.phy_clk_1x (phy_clk_1x),

.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),

.ctl_negedge_en (ctl_negedge_en),

.ctl_add_intermediate_regs (ctl_add_intermediate_regs),

.period_sel (period_sel_addr[`ADC_WE_N_PERIOD_SEL]),

.seq_ac_sel (seq_ac_sel),

.ctl_ac_h (ctl_mem_we_n_h),

.ctl_ac_l (ctl_mem_we_n_l),

.seq_ac_h (seq_we_n_h),

.seq_ac_l (seq_we_n_l),

.mem_ac (mem_we_n)

);

So I duplicated the whole block, adding the extra WE to the new DDR3 chip in the RANK:

ddr3_controller_phy_alt_mem_phy_ac# (

.POWER_UP_HIGH (1),

.DWIDTH_RATIO (DWIDTH_RATIO)

) we2_n_struct (

.clk_2x (ac_clk_2x),

.reset_2x_n (1'b1),

.phy_clk_1x (phy_clk_1x),

.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),

.ctl_negedge_en (ctl_negedge_en),

.ctl_add_intermediate_regs (ctl_add_intermediate_regs),

.period_sel (period_sel_addr[`ADC_WE_N_PERIOD_SEL]),

.seq_ac_sel (seq_ac_sel),

.ctl_ac_h (ctl_mem_we_n_h),

.ctl_ac_l (ctl_mem_we_n_l),

.seq_ac_h (seq_we_n_h),

.seq_ac_l (seq_we_n_l),

.mem_ac (mem2_we_n)

);

You have to do this with the ADDR, CAS, RAS, CKE, BA, CS_N, ODT and Reset. Its painful - but do just one, see if your error goes away for that one in particular, then the rest are easier, because you can follow the first signal you put in through each module and the others are located nearby, just make the new, extra versions.

Hope this helps anyone. What I found when trying to do this was the Data, DQS, DQ, DQSN pins all had to have their own paths, you cannot duplicate them (and this should make sense, as well). For example, I have two 16 bit DDR3 chips in my rank. The lower chip gets data(0:15) and thus DQs(0:1), DQSN(0:1), while the upper Chip gets DQ(16:31) and DQS(2:3) and DQSN(2:3)