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Altera_Forum's avatar
Altera_Forum
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15 years ago

ALTMEMPHY Logical Data Order

I am trying to create a signal integrity memory test between a Stratix IV and DDR3 DIMM. I want to specify the 72bits that are simultaneous on the bus and do that for all 8 bits of the burst. How does the 576bits of the logical data for ALTMEMPHY map to the 72bits of physical data? Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I believe its LSB to MSB. Use the example top project provided with the IP and a simulation to confirm.

    I recommend using UniPHY not AltMemPHY as this is the latest IP.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for that info. Unfortunately, I don't get to pick which PHY is used.