Honored Contributor
Honored ContributorHere is the pin connections
control interface dfi_address => ctl_addr dfi_bank => ctl_ba dfi_cas_n => ctl_casn dfi_cke => ctl_cke dfi_cs_n => ctl_csn dfi_odt => ctl_odt dfi_ras_n => ctl_rasn dfi_reset_n => ctl_rstn dfi_we_n => ctl_wen write interface dfi_wrdata => ctl_wdata dfi_wrdata_en => ctl_wdata_valid dfi_wrdata_mask => ctl_dm Also need to add logic to generate a ctl_dqs_burst signal read interface dfi_rddata_en => ctl_doing_read dfi_rddata <= ctl_rdata dfi_rddata_valid <= ctl_rdata_valid status interface dfi_init_complete <= ctl_cal_success dfi_dram_clk_disable => ctl_mem_clk_disable for ctl_dqs_burst you need to use the dfi_wrdata_en signal but delay it depending on what sort of AFI write interface you are using. Full rate, half rate, odd or even alignment. The required waveforms are listed in Altera's external memory handbook.
