Occasional Contributor
Occasional ContributorContinuing with our discussion - I am using a EP3C80F484C6N device that can support a high speed ALTLVDS_RX module. In Figure 31
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf
It is noted that the device can support an interface with the following characteristics.
fHSCLK (input Factor Min Max
clock frequency) ×10 5 437.5MHz
Yet, when I synthesize my design, I receive the following critical warning. How do I handle this warning? I see correct behavior in hardware.
Critical Warning (176575): Cannot implement PLL "DESERIALIZER_CAM:U_SENSOR_1|altlvds_rx:ALTLVDS_RX_component|DESERIALIZER_STEREOCAM_lvds_rx:auto_generated|lvds_rx_pll", because the input clock of the PLL "I_CLK_1" uses I/O standard 2.5 V and has a frequency of 360 MHz. However, the device only supports a frequency up to 250 MHz.
Critical Warning (176575): Cannot implement PLL "DESERIALIZER_CAM:U_SENSOR_0|altlvds_rx:ALTLVDS_RX_component|DESERIALIZER_STEREOCAM_lvds_rx:auto_generated|lvds_rx_pll", because the input clock of the PLL "I_CLK_0" uses I/O standard 2.5 V and has a frequency of 360 MHz. However, the device only supports a frequency up to 250 MHz.
