Honored Contributor
Honored Contributorhi, zoulzubazz.
Could you attach that two pictures again? They are too small to see clearly. --- Quote Start --- http://www.alteraforum.com/forum/attachment.php?attachmentid=10601&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=10602&stc=1 hey guys, attached is the block diagram for a deserialiser unit (deseralization factor 6) constructed using altlvds_rx megafunction. this is for cyclone ii so there is no dedicated hardware for deserialization. input data rate from ADC is 300mbps, it is in DDR format and each frame is 6 bits long making the frame clock (clkin in timing diagram) 50MHz. this frame clock is fed into a pll to generate the bit clock (rxclk) at 150 MHz. I am attaching the block diagram and a snapshot of the timing diagram for a functional simulation where the data is high for a rising edge and falling edge of the bitclock. the concern is the delay between the change in the input data (datain) and the time required to register this change at rx[0] (it takes four clock edges before rx[0] changes). is this normal? is there a way to fix this. thanks. --- Quote End ---
