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Altera_Forum
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10 years ago

ALTLVDS_RX few questions.

http://www.alteraforum.com/forum/attachment.php?attachmentid=10549&stc=1 hey guys, I have finally gathered the will to use an fpga. the plan is to use an octal adc to receive serialized dat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You should be able to, but you need to check the FPGA datasheet. There are rules about which SERDES blocks can be fed by which PLLs. If your 16 LVDS inputs cannot be fed by the same PLL, then you will have to break the 16 down into smaller blocks.

I've use 8 LVDS pairs in a block before. I could have used 16 on the same PLL in one of the Stratix IV's. I don't know about the Cyclone II's .