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Altera_Forum
Honored Contributor
Honored ContributorALTLVDS_RX few questions.
http://www.alteraforum.com/forum/attachment.php?attachmentid=10549&stc=1 hey guys, I have finally gathered the will to use an fpga. the plan is to use an octal adc to receive serialized dat...
Altera_ForumHonored Contributor
Honored ContributorYou would have 2 inputs each with a 7-bit deserialization factor. This would give you two 7 bit data buses of which one is the upper 7 bits and one is the lower 7 bits. These are then concatenated together to make the 14bit wide data bus.
Assuming you have a frame clock, then you don't use DDR as such, but use a PLL to generate the bit clock from the frame clock at a high enough frequency to clock you data stream. If the data is DDR, you may have to use the ALTLVDS module in external PLL mode and instantiate a PLL instance for your required frequencies.
