ALTLVDS_RX few questions.

You would have 2 inputs each with a 7-bit deserialization factor. This would give you two 7 bit data buses of which one is the upper 7 bits and one is the lower 7 bits. These are then concatenated together to make the 14bit wide data bus.

Assuming you have a frame clock, then you don't use DDR as such, but use a PLL to generate the bit clock from the frame clock at a high enough frequency to clock you data stream. If the data is DDR, you may have to use the ALTLVDS module in external PLL mode and instantiate a PLL instance for your required frequencies.