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Altera_Forum
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10 years ago

ALTLVDS IP: Can serdes channels be placed into different IO banks?

Hello! I'm using cycloneV and trying to place ALTLVDS IP channels into different banks. Both TX and RX IPs are used with external PLL and channels placed into a single bank works fine, but if i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I am using only one external PLL. With this, I have successfully compiled the design with placing IOs in Bank 3,4 and 5, one bank each time. It works great but if i use two banks together, design fails.

I have ran the fitter without any clock assignments like you suggested and still got the error.(Fitter has I/O placement optimization ON)

UPDATE:

I have tried with my clock constraints but no LVDS I/O constraints. Fitter compilation is successful with I/Os placed in bank 3,4, and 5. Unfortunately if I change the pins according to my development board , It fails.